Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device with a buried gate and a method for fabricating the same.
Recent fabrication processes of semiconductor devices, such as dynamic random access memory (DRAM), have been developed to increase integration density. A variety of methods have been attempted to ensure the reliability of the semiconductor devices, while increasing the integration density of the semiconductor devices through the fabrication of a buried gate. A buried gate may also be referred to as a buried word line.
A buried gate can remarkably reduce a parasitic capacitance between a word line and a bit line by burying a gate or a word line within a semiconductor substrate. Accordingly, the application of a buried gate can greatly improve the reliability of a voltage sensing operation of a semiconductor device.
Meanwhile, in a semiconductor device including a buried gate, where there is a relatively small horizontal space for the buried gate, a double-layer structure in which a low-resistance metal layer is disposed on the polysilicon layer cannot be used. Therefore, in fabricating a buried gate, a low-resistance metal layer may be used as a gate electrode, without forming a polysilicon layer on a gate dielectric layer.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device with a buried gate.
Referring to FIG. 1, the conventional semiconductor device may include a semiconductor substrate 11 in which a first region 101 and a second region 102 are defined. The first region 101 is a memory cell region, and the second region 102 is a peripheral circuit region.
Isolation layers 12 may be formed in the first region 101 and the second region 102 in order to isolate elements formed in the respective regions. The isolation layers 12 define a plurality of active regions 13 in the respective regions.
In the first region 101, the active region 13 and the isolation layer 12 may be simultaneously etched to form an active region trench 14A and an isolation layer trench 14B. Subsequently, buried gates 16, partially filling the active region trench 14A and the isolation layer trench 14B, may be formed. That is, the buried gates 16 may be formed in a portion of the active region trench 14A formed in the active region 13 and also may be formed in a portion of the isolation layer trench 14B formed in the isolation layer 12. Since the active region trench 14A and the isolation region trench 14B may be formed by simultaneously etching the active region 13 and the isolation layer 12, they may extend in the same direction.
Further, interlayer dielectric layers 17 may be formed on the buried gates 16 to gap-fill the remaining portions of the active region trench 14A and the isolation layer trench 14B. Moreover, gate dielectric layers 15 may be formed between the buried gates 16 and the active region trench 14A and the isolation layer trench 14B.
In the conventional semiconductor device described above, there is a concern regarding the characteristics of the buried gates 16. Although not shown, the buried gates 16 may be degraded during a variety of subsequent thermal processes, such as an oxidation process.